1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device.
2. Related Art
As semiconductor devices become miniaturized, a junction (diffusion layer) which is shallower and has lower resistance than before is demanded in the source/drain (SD) extension portion. In order to form a junction which is shallower and has lower resistance, it is necessary to perform heat treatment at a high temperature within a short time. However, it is difficult to meet the demand with spike rapid thermal annealing (sRTA) which is generally used.
sRTA is a heat treatment technique using lamp light. In sRTA, the holding time at peak temperature is about 0 seconds, but the wafer temperature is maintained at “peak temperature −50° C.” or more for 1 second, for example.
Then, as next-generation techniques of sRTA, techniques of heating the silicon wafer surface at 1100° C. or more on the order of milliseconds, such as Flash Lamp Annealing (hereinafter, referred to as “FLA”) and Laser Annealing (hereinafter, referred to as “LA”), are expected.
Currently, various kinds of proposals have been made as the millisecond-order annealing techniques described above (for example, refer to Japanese Laid-open Patent Publication NO. 2006-005357 and “T. Yamamoto et al., VLSI Symp. Tech., p122, 2007”.
The present inventor has recognized as follows. In such millisecond-order annealing, however, there is a problem that defects (especially, an amorphous layer used for SD extension formation of a pFET) caused at the time of ion implantation cannot be recovered since the heat treatment time is too short.
Although a process in which FLA and sRTA are combined has been reported to accelerate the recovery of defects, it has a disadvantage in that the limitation of a shallow junction is defined by sRTA. On the other hand, when an amorphous layer is not formed in the pFET, there is a disadvantage in that the activation rate drops.
In recent years, a technique of making the silicon surface amorphous before implanting SD extension impurities of the pFET is used. This is a technique of ion-implanting silicon or impurities (for example, Ge) with a larger atomic weight than silicon to the silicon surface in order to prevent channeling and also has an effect of increasing the absorption coefficient of the surface layer.
However, there are trade-offs between this technique and the effect of millisecond annealing. While it has been reported that the activation rate increases when an amorphous layer is formed at a silicon surface, many crystal defects remain in the silicon. Accordingly, there was a high possibility that problems, such as a junction leakage current, would be generated since the defects could not be recovered by only normal millisecond annealing.